International Journal of Merging Technology and Advanced Research in Computing (IJMTARC)



IJMTRAC - Volume 5 Issue 18/JUNE 2017

Manuscript Code
Title of Paper
Authors
170601

COMPUTER AIDED DESIGN AND ANALYSIS OF AN G+6 FIVE APARTMENT RESIDENTIAL COMPLEX USING STAAD.PRO

G MADHU KUMAR,Mr. P.HANMANDLU
170602

DESIGN OF FIXTURE TO OPTIMISE PROCESS PLAN OF AEROSPACE COMPONENT

DURGA BHAVANI,G. VENKATESH
170603

OPTIMIZATION IN MANUFACTURING PROCESS OF ARTILLERY FUZE BY USING DESIGNED FIXTURE

MIDIDODDI JYOTHI,VEMURI VENKATA PHANI BABU
170604

DESIGN, ANALYSIS AND MANUFACTURING OF PRESSURE VESSELS

Y.VASUDHAR,L B BHARATH RAJU
170605

SECURITY, CONTROL AND ACCESS ON IOT AND ITS THINGS

V. SRIKANTH
170606

DESIGNING AND MANUFACTURING OF TOOTH WHEEL USED IN METRO TRAINS-

B.V.M.D.N.S PAVAN, SINGHIE .G
170607

FALL ALARM AND INACTIVITY DETECTION SYSTEM DESIGN AND IMPLEMENTATION ON RASPBERRY PI

KAMA MOUNIKA, K.SONI
170608

THE EFFECTIVE GENUINE SIGNIFICANT EXCHANGE PROTOCAL FOR PNFS

GODDE. VARAMMA,GURRAPU.NEELIMA
170609

AN ADAPTIVE CURRENT SOURCE INVERTER FOR HARMONIC ENERGY COHORTS

A DEVI SHALINI,G RATNA KUMARI,RAMAVATH SHANKAR NAIK
170610

A COMPENSATION TECHNIQUES OF RAILWAY POWER CONDITIONER FOR RAILWAY POWER SYSTEM

ANKALA HAREESH KUMAR,G RATNA KUMARI,RAMAVATH SHANKAR NAIK
170611

ANALYSIS OF DIFFERENT TOPOLOGIES FOR ACTIV POWER FACTOR CORRECTION IN DC – DC CONVERTERS

GUNTAKANDLA VIKRAM,M RAVINDAR,RAMAVATH SHANKAR NAIK
170612

A DESIGN OF ULTRA CAPACITOR FOR IMPROVING POWER QUALITY OF DISTRIBUTION GRID BY AN INTEGRATED DYNAMIC VOLTAGE RESTORER

M NAGARAJU,RAMAVATH SHANKAR NAIK
170613

ENHANCEMENT OF POWER QUALITY IMPROVEMENT GRID CONNECTED DUAL VOLTAGE SOURCE INVERTER

MANTHENA RAGHUVARAN,G RATNA KUMARI,RAMAVATH SHANKAR NAIK
170614

Fault current and overvoltage limitation in a distribution network with distributed Generation units through superconducting fault current limiter

DESHAVENI DEEPAK, M RAVINDAR, RAMAVATH SHANKAR NAIK
170615

GRID VOLTAGE REGULATION BY USING PV BASED DUAL TOPOLOGY OF THE UNIFIED POWER QUALITY CONDITIONER(IUPQC)

M PADMAJA, RAMAVATH SHANKAR NAIK
170616

IMPROVEMENT OF POWER QUALITY BY USING A ROBUST HYBRID SERIES ACTIVE POWER FILTER

POLAGONI SHIVAJI,M RAVINDAR,RAMAVATH SHANKAR NAIK
170617

UNDER DISTORTED GRID VOLTAGE DIRECT POWER CONTROL OF DOUBLY FED INDUCTION GENERATOR

SHAGANTI PRAVEEN,G RATNA KUMARI,RAMAVATH SHANKAR NAIK
170618

TRACKING THE MAXIMUM POWER POINT WITH ARTIFICIAL NEURAL NETWORK

CHINTHAMOLA VISHNUVARDHAN REDDY,RAMAVATH SHANKAR NAIK
170619

GRID SYNCHRONIZATION METHOD FOR THREE PHASE THREE WIRE NETWORKS UNDER GRID FAULT CONDITION

NELAGUDUTI UPENDAR,RAMAVATH SHANKAR NAIK
170620

ENHANCEMENT OF POWER QUALITY USING SELF SUPPORTED DVR

KALYADAPU RAJASHEKAR,RAMAVATH SHANKAR NAIK
170621

AN EFICIENT CONSTRUCTION CALLED DEYPOS, TO ACHIEVE DYNAMIC POS AND SECURE CROSS-USER DEDUPLICATION

RAGHUVEER REDDY
170622

REDUCTION OF STATIC POWER BY USING BIASING AND BODY BIASING TECHNIQUES

B MOUNIKA,K BHAVANI
170623

A FRAMEWORK TO DETECT AND CORRECT ERRORS IN CIRCUITS

B SANDHYA,AYESHA BEGUM
170624

POST OPTIMIZATION OF A CLOCK TREE FOR VIGOR GIVE NOISE REDUCTION

E Saresh Kumar,M SreeChandana
170625

POWER EFFICIENT PARALLEL CHIEN SEARCH ARCHITECTURE USING A TWO STEP APPROACH IN RS CODES

M ANJANEYULU,K BHAVANI
170626

ANALYSIS OF DATA HIDING TECHNIQUES IN ENCRYPTED IMAGES - A SURVEY

G MOUNIKA,G SATHYA PRABHA
170627

ADOPTING NR4SD+ SCHEME INTO DSP

R RAMYAM,M SREECHANDANA
170628

A NOVEL FPGA DESIGN WITH HYBRID LUT/MULTIPLEXER ARCHITECTURE

A SHANKAR NAYAK,P V VARAPRASAD RAO
170629

DESIGNING A LESS ENERGY AND LESS-SIZE SHIFT REGISTER FOR VLSI CIRCUIT USING PULSED HANDLES

T SARASWATHI,P V VARAPRASAD RAO